The advancement of Artificial Intelligence (AI) and its rapid deployment on a broad spectrum of platforms relies on both design quality and design efficiency of circuits, systems, and algorithms. Moreover, security and robustness concerns arise at both hardware and software levels in some critical applications of AI models. Cross-layer optimization becomes essential to achieve these goals. In this talk, we first introduce circuit-level innovations for emerging AI models and devices, including the popular processing-in-memory (PIM) computing primitives centered on various new types of nanodevices. After that, we discuss efficient architecture design atop these innovations, such as multiplier array, systolic array, PIM-based deep neural network (DNN), and spiking neural network (SNN) pipelines. Then we present hardware-friendly model compression techniques to optimize the quality-efficiency trade-off on AI models. We also introduce several efficient distributed learning frameworks that enable the scalability of AI systems. Finally, we show some approaches to resolve the challenges introduced by the imperfect characteristics of semiconductor devices and the security concerns in real-world systems. We hope our talk will offer the audience a comprehensive overview of a full-stack design and optimization of efficient AI circuits and systems (AI-CAS) solutions.
Speaker(s): Dr. Yiran Chen,
Agenda:
730 PM – login to google meet and start of presentation
900 PM – end of event
Virtual: https://events.vtools.ieee.org/m/369615