Virtual Events

Continuing Education credit registration fee of $7 to obtain the certificate. Virtual: https://events.vtools.ieee.org/m/493913

Abstract: Latest SerDes Technologies such as 200G Ethernet, PCIe Gen 7, etc. — A Signal Integrity Perspective As SerDes technologies push the boundaries of data rates—reaching 200G Ethernet, PCIe Gen 7, and beyond—Signal Integrity (SI) becomes a critical factor in ensuring reliable high-speed communication. This talk focuses on the latest advancements in SerDes and their implications for SI across system design, PCB layout, and interconnect strategies. We will explore how PAM4 modulation, multi-level signaling, and lane aggregation impact channel performance, and how engineers are addressing challenges like crosstalk, return loss, jitter, and inter-symbol interference (ISI). Special attention will be given to equalization techniques, FEC, and advanced simulation models that help predict and mitigate SI issues in real-world designs. Key topics include: - SI challenges in 200G Ethernet and PCIe Gen 7 - Impact of connector and via design on high-speed channels - Role of materials, stack-up, and routing in maintaining signal fidelity - Measurement and validation techniques: TDR, S-parameters, eye diagrams - Co-design strategies for SerDes PHYs and PCB interconnects This session is ideal for hardware designers, SI engineers, and system architects looking to stay ahead in the rapidly evolving landscape of high-speed serial interfaces. Speaker(s): Randy, Virtual: https://events.vtools.ieee.org/m/505840