(Sep. 26, 2025) Enabling Energy-Efficient Artificial Intelligence Hardware with Spintronics

Zoom link: https://argonne.zoomgov.com/j/1602717824?pwd=NZxbKVS1Ac24psobtx2C90Pa9Jpn2r.1
Speaker:
Prof. Cheng Wang
Department of Electrical and Computer Engineering, Iowa State University
Date & Time:
September 26, 1:00 pm – 2:00 pm, CST
Abstract:
The pursuit of high-performance and energy-efficient computing for artificial intelligence (AI) opens up exciting opportunities for emerging memories and unconventional architectures such as analog in-memory computing (IMC). To maximize the potential of such emerging computing technologies, innovations across the stack (from devices to systems) are needed. In this talk, I will share some of our group’s recent co-design efforts in exploiting spintronic components for developing efficient deep neural network (DNN) hardware. First, a multi-level spintronic synaptic device based on a composite magnetic tunnel junction (MTJ) is proposed and analyzed in simulation. By integrating a standard MTJ free layer exchange coupled with a granular magnetic nanostructure, multiple near-continuous nonvolatile resistive states can be induced thanks to the distribution of the energy barrier among individual magnetic grains. Second, we exploit stochastic MTJs as the core components for the array-level partial sums (PS) in crossbar architecture and for the processing engines in near-memory systolic arrays. Leveraging the probabilistic switching of spin-orbit torque (SOT) MTJs, the proposed PS processing eliminates the costly Analog-Digital Conversion in crossbar IMC, leading to significant improvement in energy and area efficiency. We further show that the accuracy loss due to quantization error can be mitigated by a newly developed PS-quantization-aware DNN training methodology. Our device-to-system co-optimization research demonstrates exciting opportunities for spintronics in developing next-generation energy-efficient intelligent computing systems. I will conclude my talk with discussions on the potential of co-designing spintronics for various unconventional computational functionalities.
Biography:
Cheng Wang is an Assistant Professor of Electrical and Computer Engineering at Iowa State University. Cheng received his B.S. degree in physics from Peking University in 2009 and completed his Ph.D. from the University of Texas at Austin in 2016, with his dissertation on exploring spintronic and memristive devices. Prior to joining Iowa State, Cheng was a Research Scientist at the Center for Brain-inspired Computing Enabling (C-BRIC) at Purdue University. Cheng worked as a Staff R&D Engineer at Seagate Research Center from 2016 to 2019, where he designed high-density magneto-electronic memory and storage technologies. His current research interests include machine learning hardware acceleration and energy-efficient neuromorphic computing with emerging technologies and architectures. He has served on the Technical Program Committee for beyond-CMOS and emerging technologies for IEEE/ACM Design Automation Conference (DAC), International Conference on Computer-Aided Design (ICCAD), and the Great Lakes Symposium on VLSI. He is a recipient of the NSF CAREER Award, Seagate FRC Technical Award, and Best Paper Award for the IEEE International Conference on Rebooting Computing (ICRC).
Co-sponsored by: IEEE Chicago, IEEE NTC Young Professionals
9700 S Cass Ave, Bldg. 222, A229, LEMONT, Illinois, United States, 60439, Virtual: https://events.vtools.ieee.org/m/500597